Field programmable processor arrays

ABSTRACT

An integrated circuit has a field programmable circuit region arranged as a generally rectangular array of rows and columns of circuit areas. Some of the circuit areas each provide a respective processing unit for performing operations on data on at least one respective input signal path to provide data on at least one respective output signal path. Others of the circuit areas each provide a respective switching section; and the processing units and the switching sections are arranged alternately in each row and in each column. Each of a substantial proportion of the switching sections provides a programmable connection between at least some of the signal paths of those of the processing units adjacent that switching section in the same column and in the same row. A dense layout can be obtained with efficient local interconnections, especially in the case where one or more of the processing units has a plural-bit input and/or plural-bit output, and at least some of the signal paths are provided by respective plural-bit busses.

BACKGROUND OF THE INVENTION

This invention relates to field programmable processor arrays, that is,arrays of processing units which are selectively connectable by signalpaths one to another, and in particular to such arrays which areprovided as integrated circuits.

The problems with which the present invention (or at least preferredembodiments of it) is concerned are to provide a dense circuit layout,efficient interconnections between the processing units and flexibilityin the manner in which the processing units may be interconnected.

SUMMARY OF THE INVENTION

In accordance with the present invention, there is provided anintegrated circuit having a field programmable circuit region arrangedas a generally rectangular array of rows and columns of circuit areas,wherein: some of the circuit areas each provide a respective processingunit (such as an arithmetic logic unit) for performing operations ondata on at least one respective input signal path to provide data on atleast one respective output signal path; others of the circuit areaseach provide a respective switching section; the processing units andthe switching sections are arranged alternately in each row and in eachcolumn; and each of a substantial proportion (and preferably all) of theswitching sections provides a programmable connection between at leastsome of the signal paths of those of the processing units adjacent thatswitching section in the same column and in the same row. By arrangingthe circuit in this way, a dense layout can be obtained with efficientlocal interconnections, especially in the case where one or more of theprocessing units has a plural-bit input and/or a plural-bit output, andat least some of the signal paths are provided by respective plural-bitbusses.

A first type of the connections provided by the switching sections arebetween such signal paths which may be generally collinear with orparallel to each other, allowing the paths to be selectably concatenatedto produce longer connections. In this case and in the case where atleast one of the processing units and the processing units adjacentthereto each have a first input, a second input and an output; theoutput of said one processing unit is preferably connectable: by such afirst type of connection to the first input of the next processing unitin one direction in the same row; by such a first type of connection tothe first input of the next processing unit in the one direction in thesame column; by such a first type of connection to the second input ofthe next processing unit in the opposite direction in the same row; andby such a first type of connection to the second input of the nextprocessing unit in the opposite direction in the same column. In thisway, the output of a first processing unit can be selectably passed toany of the four adjacent processing units in the same row or column (“asecond processing unit”), where it can be processed and then passed backto the first processing unit or passed on to any of the other threeadjacent processing units adjacent the second processing unit.

A second type of the connections provided by the switching sections arebetween such signal paths which may be generally orthogonal to eachother. Thus the signal paths can change direction to enable flexiblerouting. In this case and in the case where at least one of theprocessing units and the processing units adjacent thereto each have afirst input, a second input and an output, the output of said oneprocessing unit is preferably connectable: by such a second type ofconnection in the same column to the first input of the diagonallyadjacent processing unit in said one row direction and said one columndirection; by such a second type of connection in the same row to thefirst input of the diagonally adjacent processing unit in said oppositerow direction and said one column direction; by such a second type ofconnection in the same column to the second input of the diagonallyadjacent processing unit in said opposite row direction and saidopposite column direction; and by such a second type of connection inthe same row to the second input of the diagonally adjacent processingunit in said one row direction and said opposite column direction. Thus,the output from a first processing unit can be selectably routed to thefirst inputs of two of the diagonally adjacent processing units, and tothe second inputs of the other two diagonally adjacent processing units.

Preferably substantially all of the input and output signal paths areoriented in directions substantially parallel to the rows or thecolumns, thus enabling a dense layout to be achieved.

The integrated circuit preferably further comprises a plurality of interswitching section signal paths, each of which extends from a respectivefirst one of the switching sections to a respective second one of theswitching sections in the same row in a direction primarily generallyparallel to that row, or in the same column in a direction primarilygenerally parallel to that column, each of the inter switching sectionsignal paths being programmably connectable by the respective firstswitching section to others of the signal paths at that first switchingsection, and being programmably connectable by the respective secondswitching section to others of the signal paths at that second switchingsection. Accordingly, medium and long range connections can beselectably provided.

For one type of the inter switching section signal paths, there may beno such switching sections in the respective row or column between therespective first and second switching sections.

For another type of the inter switching section signal paths, therespective first and second switching sections may have a number(preferably one less than a power of two) of other such switchingsections therebetween in the respective row or column. Thus, long rangeconnections are provided reducing the number of intermediate switcheswhich may be required, and accordingly reducing the propagation delaywhich would be caused thereby.

For a further type of the inter switching section signal paths, eachsignal path may have a spine portion extending in a direction generallyparallel to the respective row or column and first and second endportions each extending in a direction generally orthogonal to therespective row or column and interconnecting the spine portion and therespective first and second switching sections, respectively. Since thespine portions do not connect to the switches directly, the choice ofthe physical position of the conductors in the spine portion isflexible, and this flexibility enables denser layouts to be achieved.For at least some of the inter switching section signal paths of saidfurther type, the respective first and second switching sections mayhave a number (preferably one less than a power of two) of other suchswitching sections therebetween in the respective row or column. Thus,long range connections are provided reducing the number of intermediateswitches which may be required, and accordingly reducing the propagationdelay which would be caused thereby. At least some of the interswitching section signal paths of said further type preferably each haveat least one tap portion extending in a direction generally orthogonalto the respective row or column and interconnecting the spine portionand a respective such other switching section. Accordingly, even greaterflexibility is provided.

At least some of the switching sections preferably each include arespective register and/or buffer having an input and an output eachswitchably connectable to at least some of the signal paths at thatswitching section. This allows signals to be retimed or buffered withoutusing one of the processing units for that purpose. Retiming andbuffering of time-critical signals allows configurations to run athigher clock speeds, increasing the rate of operation.

BRIEF DESCRIPTION OF THE DRAWINGS

A specific embodiment of the present invention will now be described, byway of example, with reference to the accompanying drawings, in which:

FIG. 1 shows part of a processor array, illustrating six switchingsections and the locations of six arithmetic logic units;

FIG. 2 is a diagram of part of the arrangement shown in FIG. 1 on alarger scale, illustrating one of the switching sections and one of thelocations of the arithmetic logic units;

FIG. 3 shows part of the processor array shown in FIG. 1 on a smallerscale, illustrating the locations of the arithmetic logic units and“vertical” busses extending across them;

FIG. 4 is similar to FIG. 3, but illustrating “horizontal” bussesextending across the locations of the arithmetic logic units;

FIG. 5 shows the interconnections between the the busses of FIGS. 2, 3and 4 at the location of one of the arithmetic logic units;

FIG. 6A shows in detail the circuitry of one type of programmable switchin the switching sections, for connecting a pair of 4-bit busses whichcross each other;

FIG. 6B shows in detail the circuitry of another type of programmableswitch in the switching sections, for connecting a pair of 4-bit busseswhich meet each other end to end;

FIG. 6C shows in detail the circuitry of another type of programmableswitch in the switching sections, for connecting carry-bit busses;

FIG. 7 shows the circuitry of a series of NOR gates which may be used inthe programmable switches of FIGS. 5 and 6;

FIG. 8 shows a modification to the circuitry of FIG. 7;

FIG. 9 shows a buffer and register which may be used in each switchingsection;

FIG. 10 is a schematic drawing illustrating how enable signals may bedistributed to the programmable switches in the switching sections; and

FIG. 11 shows in more detail the circuitry of the arrangement shown inFIG. 10.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the following description, the terms “horizontal”, “vertical”,“North”, “South”, “East” and “West” have been used to assist in anunderstanding of relative directions, but their use is not intended toimply any restriction on the absolute orientation of the embodiment ofthe invention.

The processor array which forms the embodiment of the invention isprovided in an integrated circuit. At one level, the processor array isformed by a rectangular (and preferably square) array of “tiles” 10, oneof which is shown bounded by a thick line in FIG. 1. Any appropriatenumber of tiles may be employed, for example in a 16×16, 32×32 or 64×64array. Each tile 10 is rectangular (and preferably square) and isdivided into four circuit areas. It is preferable for these tiles to belogically square (to provide symmetry in connection), although it is ofless significance that they be physically square (this may have someadvantage in providing symmetry in timing, but this will generally beless likely to be of significance). Two of the circuit areas 12, whichare diagonally opposed in the tile 10, provide the locations for twoarithmetic logic units (“ALUs”). The other two circuit areas, which arediagonally opposed in the tile 10, provide the locations for a pair ofswitching sections 14.

Referring to FIGS. 1 and 2, each ALU has a first pair of 4-bit inputs a,which are directly connected within the ALU, a second pair of 4-bitinputs b, which are also directly connected within the ALU, and four4-bit outputs f, which are directly connected within the ALU. Each ALUalso has an independent pair of 1-bit carry inputs hci, vci, and a pairof 1-bit carry outputs co, which are directly connected within the ALU.The ALU can perform standard operations on the input signals a, b, hci,vci to produce the output signals f, co, such as add, subtract, AND,NAND, OR, NOR, XOR, NXOR and multiplexing and optionally can registerthe result of the operation. The instructions to the ALUs may beprovided from respective 4-bit memory cells whose values can be set viathe “H-tree” structure described below, or may be provided on the bussystem which will be described below.

At the level shown in FIGS. 1 and 2, each switching section 14 has eightbusses extending across it horizontally, and eight busses extendingacross it vertically, thus forming an 8×8 rectangular array of 64crossing points, which have been numbered in FIG. 2 with Cartesianco-ordinates. All of the busses have a width of four bits, with theexception of the carry bus vc at X=4 and the carry bus hc at Y=3, whichhave a width of one bit. At many of the crossing points, a 4-gangprogrammable switch 16 is provided which can selectively connect the twobusses at that crossing point. At some of the crossing points, a 4-gangprogrammable switch 18 is provided which can selectively connect twobusses which meet end to end at that crossing point, without anyconnection to the bus at right angles thereto. At the crossing point at(4, 3), a programmable switch 20 (for example as shown in FIG. 6C) isprovided which can selectively connect the carry busses vc, hc whichcross at right angles at that point.

The horizontal busses in the switching section 14 will now be described.

At Y=0, busses h2s are connectable by programmable switches 16 to thevertical busses at X=0, 1, 2, 5, 6. The busses h2s have a length of twotiles and are connectable end to end in every other switching section 14by a programmable switch 18 at (4, 0).

At Y=1, a bus be extending from an input b of the ALU to the West isconnectable by switches 16 to the vertical busses at X=0, 1, 2, 3. Also,a bus fw extending from an output f of the ALU to the East isconnectable by switches 16 to the vertical busses at X=5, 6, 7. The endsof the busses be, fw are connectable by a programmable switch 18 at (4,1).

At Y=2, a bus hregs is connectable by programmable switches 16 to thevertical busses at X=1, 2, 3, 5, 6, 7.

At Y=3, a bus hco extends from the carry output co of the ALU to theWest to a programmable switch 20 at (4, 3), which can connect the bushco (a) to a carry bus hci extending to the carry input hci of the ALUto the East or (b) to a carry bus vci extending to the carry input vciof the ALU to the South.

At Y=4, a bus hregn is connectable by programmable switches 16 to thevertical busses at X=0, 1,2,3,5,6.

At Y=5, busses h1 are connectable to the vertical busses at X=0, 1, 2,3, 5, 6, 7. The busses h1 have a length of one tile and are connectableend to end in each switching section 14 by a programmable switch 18 at(4, 5).

At Y=6, a bus fe extending from an output f of the ALU to the West isconnectable by switches 16 to the vertical busses at X=0, 1, 2, 3. Also,a bus aw extending from an input a of the ALU to the East is connectableby switches 16 to the vertical busses at X=5, 6, 7. The ends of thebusses fe, aw are connectable by a programmable switch 18 at (4, 6).

At Y=7, busses h2n are connectable by programmable switches 16 to thevertical busses at X=1, 2, 3, 6, 7. The busses h2n have a length of twotiles and are connectable end to end in every other switching section 14by a programmable switch 18 at (4, 7), staggered with respect to theprogrammable switches 18 connecting the busses h2s at (4, 0).

The vertical busses in the switching section 14 will now be described.

At X=0, busses v2w are connectable by programmable switches 16 to thehorizontal busses at Y=0, 1, 4, 5, 6. The busses v2w have a length oftwo tiles and are connectable end to end in every other switchingsection 14 by a programmable switch 18 at (0, 3).

At X=1, a bus fn extending from an output f of the ALU to the South isconnectable by programmable switches 16 to the horizontal busses at Y=0,1, 2. Also, a bus bs extending from an input b of the ALU to the Northis connectable by switches 16 to the horizontal busses at Y=4, 5, 6, 7.The ends of the busses fn, bs are connectable by a programmable switch18 at (1, 3).

At X=2, busses v1 are connectable to the horizontal busses at Y=0, 1, 2,4, 5, 6, 7. The busses v1 have a length of one tile and are connectableend to end in each switching section 14 by a programmable switch 18 at(2, 3).

At X=3, a bus vregw is connectable by programmable switches 16 to thehorizontal busses at Y=1, 2, 4, 5, 6, 7.

At X=4, a bus vco extends from the carry output co of the ALU to theNorth to the programmable switch 20 at (4, 3), which can connect the busvco (a) to the carry bus hci extending to the carry input hci of the ALUto the East or (b) to the carry bus vci extending to the carry input vciof the ALU to the South.

At X=5, a bus vrege is connectable by programmable switches 16 to thehorizontal busses at Y=0, 1, 2, 4, 5, 6.

At X=6, a bus an extending from an input a of the ALU to the South isconnectable by switches 16 to the horizontal busses at Y=0, 1, 2. Also,a bus fs extending from an output f of the ALU to the North isconnectable by programmable switches 16 to the horizontal busses at Y=4,5, 6, 7. The ends of the busses an, fs are connectable by a programmableswitch 18 at (6, 3).

At X=7, busses v2e are connectable by programmable switches 16 to thehorizontal busses at Y=1, 2, 5, 6, 7. The busses v2e have a length oftwo tiles and are connectable end to end in every other switchingsection 14 by a programmable switch 18 at (7, 3) staggered with respectto the programmable switches 18 connecting the busses v2w at (0, 3).

As shown in FIG. 2, the busses bs, vco, fs are connected to input b,output co and output f, respectively, of the ALU to the North of theswitching section 14. Also, the busses fe, hco, be are connected to theoutput f, output co and input b of the ALU, respectively, to the West ofthe switching section 14. Furthermore, the busses aw, hci, fw areconnected to the input a, input ci and output f, respectively, of theALU to the East of the switching section 14. Moreover, the busses fn,vci, an are connected to the output f, input ci and input a,respectively, of the ALU to the south of the switching section 14.

In addition to these connections, the busses vregw, vrege are connectedvia respective programmable switches 18 to 4-bit connection points vtsw,vtse, respectively, (shown by crosses in FIG. 2) in the area 12 of theALU to the North of the switching section 14. Also, the busses hregs,hregn are connected via respective programmable switches 18 to 4-bitconnection points htse, htne, respectively, in the area 12 of the ALU tothe West of the switching section 14. Furthermore, the busses hregs,hregn are connected via respective programmable switches 18 to 4-bitconnection points htsw, htnw, respectively, in the area 12 of the ALU tothe East of the switching section 14. Moreover, the busses vregw, vregeare connected via respective programmable switches 18 to 4-bitconnection points vtnw, vtne, respectively, in the area 12 of the ALU tothe south of the switching section 14. These connection points vtnw,vtne, htne, htse, vtse, vtsw, htsw, htnw will be described below infurther detail with reference to FIGS. 3 to 5.

Also, as shown in FIG. 2, the busses hregn, vrege, hregs, vre gw haverespective 4-bit connection points 22 (shown by small squares in FIG. 2)which will be described below in further detail with reference to FIG.9.

FIG. 3 shows one level of interconnections between the locations of thearithmetic logic units, which are illustrated by squares with roundedcorners. A group of four 4-bit busses v8, v4w, v4e, v16 extendvertically across each column of ALU locations 12. The leftmost bus v8in each group is in segments, each having a length generally of eighttiles. The leftmost but one bus v4w in each group is in segments, eachhaving a length generally of four tiles. The rightmost but one bus v4ein each group is in segments, again each having a length generally offour tiles, but offset by two tiles from the leftmost but one bus v4w.The rightmost bus v16 in each group is in segments, each having a lengthgenerally of sixteen tiles. At the top edge of the array, which is atthe top of FIG. 4, and at the bottom edge the lengths of the segmentsmay be slightly greater than or shorter than specified above.

Referring to FIGS. 3 and 5, where each group of four busses v8, v4w,v4e, v16 crosses each ALU location 12, four 4-bit tap connections aremade at the connection points htnw, htsw, htse, htne. The ends of thebus segments take priority in being so connected over a connection to abus segment which crosses the ALU location.

Similarly, as shown in FIGS. 4 and 5, a group of four 4-bit busses h8,h4n, h4s, h16 extend horizontally across each row of ALU locations 12.The uppermost bus h8 in each group is in segments, each having a lengthgenerally of eight tiles. The uppermost but one bus h4n in each group isin segments, each having a length generally of four tiles. The lowermostbut one bus h4s in each group is in segments, again each having a lengthgenerally of four tiles, but offset by two tiles from the uppermost butone bus h4n. The lowermost bus h16 in each group is in segments, eachhaving a length generally of sixteen tiles. At the left hand edge of thearray, which is at the left of FIG. 4, and at the right hand edge thelengths of the segments may be slightly greater than or shorter thanspecified above. Where each group of busses h8, h4n, h4s, h16 crosseseach ALU location 12, a further four 4-bit tap connections are made atthe connection points vtnw, vtsw, vtse, vtne. The ends of the bussegments take priority in being so connected over a connection to a bussegment which crosses the ALU location.

As shown in FIG. 5, the connection points htnw, htsw, htne, htse areconnected via programmable switches to the busses hregn, hregs of theswitching sections to the West and the East of the ALU location. Also,the connection points vtnw, vtne, vtsw, vtse are connected viaprogrammable switches to the busses vregw, vrege of the switchingsections to the North and the South of the ALU location.

The programmable connections 16 between pairs of 4-bit busses whichcross at right angles will now be described with reference to FIG. 6A.The conductors of the horizontal busses are denoted as x0, x1, x2, x3,and the conductors of the vertical busses are denoted as y0, y1, y2, y3.Between each pair of conductors of the same bit significance, arespective transistor 160, 161, 162, 163 is provided. The gates of thetransistors 160, 161, 162, 163 are connected in common to the output ofa NOR gate 16 g, which receives as its two inputs an inverted ENABLEsignal from a single bit memory cell, which may be shared by a group ofthe switches, and the inverted content of a single bit memory cell 24.Accordingly, only when the ENABLE signal is high and the content of thememory cell 24 is high, the conductors x0, x1, x2, x3 are connected bythe transistors 160, 161, 162, 163, respectively, to the conductors y0,y1, y2, y3, respectively.

The programmable connections 18 between pairs of 4-bit busses which meeteach other end to end in line will now be described with reference toFIG. 6B. The conductors of one bus are denoted as x10, x11, x12, x13,and the conductors of the other bus are denoted as x20, x21, x22, x23.Between each pair of conductors of the same bit significance, arespective transistor 180, 181, 182, 183 is provided. The gates of thetransistors 180, 181, 182, 183 are connected in common to the output ofa NOR gate 18 g, which receives as its two inputs an inverted ENABLEsignal from a single bit memory cell, which may be shared by a group ofthe switches, and the inverted content of a single bit memory cell 24.Accordingly, only when the ENABLE signal is high and the content of thememory cell 24 is high, the conductors x10, x11, x12, x13 are connectedby the transistors 180, 181, 182, 183, respectively, to the conductorsx20, x21, x22, x23, respectively.

The programmable connections 20 between the carry conductorshco,vco,hci,vci will now be described with reference to FIG. 6C. Thehorizontal carry output conductor hco is connected to the horizontalcarry input conductor hci and the vertical carry input conductor vci viatransistors 20 hh, 20 hv, respectively. Furthermore, the vertical carryoutput conductor vco is connected to the vertical carry input conductorvci and the horizontal carry input conductor hci via transistors 20 vv,20 vh, respectively. The gates of the transistors 20 hh, 20 vv areconnected in common to the output of an inverter 20 i, and the gates ofthe transistors 20 hv, 20 vh and the input to the inverter 20 i areconnected to the output of a NOR gate 20 g. The NOR gate 20 g receivesas its two inputs an inverted ENABLE signal from a single bit memorycell, which may be shared by a group of the switches, and the invertedcontent of a single bit memory cell 24. Accordingly, when the ENABLEsignal is high, the conductors hco, vco are connected to the conductorshci, vci, respectively, or to the conductors vci, hci, respectively, independence upon the content of the memory cell 24.

It will be noted that each of the switchable connections 16, 18, 20described with reference to FIGS. 6A to 6C includes a NOR gate 16 g, 18g, 20 g. As shown in FIG. 7, a NOR gate 16 g is typically formed by fourtransistors 16 g 1, 16 g 2, 16 g 3, 16 g 4, two 16 g 1, 16 g 3 of whichare responsive to the inverted ENABLE signal, and two 16 g 2, 16 g 4 ofwhich are responsive to the inverted content of the memory cell 24. Inthe embodiment of the invention, it is desirable that a group of theswitchable collections 16, 18, 20 may be disabled in common, without anyneed for only part of such a group to be disabled. Such a group mightconsist of all of the switchable connections in one switching section14, all of the switchable connections in the two switching sections 14in a particular tile, or all of the switchable connections in a largerarea of the array. In this case, the transistor 16 g 1 may be madecommon to all of the switchable connections 16, 18, 20 in the group, asshown in FIG. 8. This enables a 25% less one saving in the number oftransistors required for the gates, but does require a further conductorlinking the gate, as shown in FIG. 8.

The man skilled in the art will appreciate that the structures depictedin FIGS. 7 and 8 can be modified for optimisation. For example, thearrangement of FIGS. 7 and 8 would not fully exploit memory cells 24designed to return both a stored value and a complement of that storedvalue. Use of the complement obtained from such cells 24 could be usedto obviate any need for both the ENABLE and inverted ENABLE signals tobe carried to all of the switchable connections in a group, as is thecase in FIG. 8. As mentioned above with reference to FIGS. 1 and 2, ateach switching section 14, the busses hregn, hregs, vregw, vrege areconnected by respective 4-bit connections 22 to a register or buffercircuit, and this circuit will now be described in more detail withreference to FIG. 9. The four connections 22 are each connected torespective inputs of a multiplexer 26. The multiplexer 26 th selects oneof the inputs as an output, which is supplied to a register or buffer28. The output of the register or buffer 28 is supplied to fourtri-state buffers 30 s, 30 w, 30 n, 30 e, which are connected back tothe connections 22 to the busses hregs, vregw, hregn, vrege,respectively. In the case where a buffer 28 is used, the 4-bit signal ona selected one of the busses hregs, vregw, hregn, vrege is amplified andsupplied to another selected one of the busses hregs, vregw, hregn,vrege. In the case where a register 28 is used, the 4-bit signal on aselected one of the busses hregs, vregw, hregn, vrege is amplified andsupplied to any selected one of the busses hregs, vregw, hregn, vregeafter the next active clock edge.

It will be appreciated that the arrangement described above providesgreat flexibility in the routing of signals around and across the array.With appropriate setting of the switches 16, 18, 20 using the memorycells 24 and with appropriate setting of the multiplexers 26 andregisters or buffers 28, signals can been sent over large distances,primarily using the busses v16, h16, v8, h8, v4e, v4w, h4n, h4s from theedge of the array to a particular ALU, between ALUs, and from aparticular ALU to the edge of the array. These busses can be joinedtogether in line, or at right angles, by the switching sections 14, withamplification by the registers or buffers 28 in order to reducepropagation delays, and with pipeline stages introduced by the registers28. Also, these busses can be tapped part way along their lengths, sothat the siting of the ALUs to perform a particular processing operationis not completely dictated by the lengths of the busses, and so thatsignals can be distributed to more than one ALU. Furthermore, theshorter length busses described with reference to FIGS. 1 and 2 can beused to route signals between the switching sections 14 and the ALUs,and to send signals primarily over shorter distances, for example fromone ALU to an adjacent ALU in the same row or column, or diagonallyadjacent, even though the busses extend horizontally or vertically.Again, the registers or buffers 28 can be used to amplify the signals orintroduce programmable delays into them.

In the arrangement described above, the memory cells 24 are distributedacross the array to the same extent as the switching sections 14 and theALU locations 12. Each memory cell 24 is disposed adjacent the switch orswitches, multiplexer, register or buffer which it controls. Thisenables a high circuit density be achieved.

A description will now be made of the manner in which data is written toor read from the memory cells 24, the way in which the ENABLE signalsfor the programmable switches 16, 18, 20 are written to their memorycells, the way in which instructions, and possibly constants, aredistributed to the ALUs, and the way in which other control signals,such as a clock signal, are transmitted across the array. For all ofthese functions, an “H-tree” structure (which is known per se) may beemployed as shown in FIG. 10. Referring to FIGS. 10 and 11, in order todistribute an ENABLE signal to any of 64 locations in the example shown,the ENABLE signal 30 a and a 6-bit address 32 a for it are supplied to adecoder 34 a. The decoder 34 a determines which of the four branchesfrom it leads to the address and supplies an ENABLE signal 30 b to afurther decoder 34 b in that branch, together with a 4-bit address 32 bto the decoders 34 b in all four branches. The decoder 34 b receivingthe ENABLE signal 30 b determines which of the four branches from itleads to the required address and supplies an ENABLE signal 30 c to afurther decoder 34 c in that branch, together with a 4-bit address 32 cto the decoders 34 c in all four branches. The decoder 34 c receivingthe ENABLE signal 30 c then supplies the ENABLE signal 34 d to therequired address where it can be stored in a single bit memory cell. Anadvantage of the H-tree structure is that the lengths of the signalpaths to all of the destinations are approximately equal, which isparticularly advantageous in the case of the clock signal.

A great advantage of the arrangement described above is that groups ofthe memory cells 24 in for example one switching section 14, or in thetwo switching sections in one tile, or in the switching sections in asub-array of the tiles may be disabled en bloc by the inverted ENABLEsignals so that the contents of those memory cells do not affect theassociated switches. It is then possible for those memory cells 24 to beused as “user” memory by an application, rather than being used forconfiguring the wiring of the array.

The embodiment of the invention has been described merely by way ofexample, and many modifications and developments may be made in keepingwith the present invention. For example, the embodiment employs ALUs asthe processing units, but other processing units may additionally oralternatively be used, for example look-up tables, programmable logicarrays and/or self-contained CPUs which are able to fetch their owninstructions.

Furthermore, the embodiment has been described as if the whole array iscovered by ALUs and switching sections. However, other types of sectionmay be included in the array. For example, a sub-array might be composedof a 4×4 arrangement of tiles of ALUs and switching sections asdescribed above, and the array might be composed of such sub-arrays andmemory in a 4×4 array, or such sub-arrays and RISC CPUs in a 4×4 array.

In the embodiment described above, each ALU location is square, and eachswitching section is square and of the same size as the ALU locations,but it should be noted that the controllable switches 18 in the registerbusses vregw, vrege, hregn, hregs encroach into the square outline ofthe ALU locations. The ALU locations need not be of the same size as theswitching sections, and in particular may be smaller, thus permittingone or more busses to pass horizontally or vertically directly from oneswitching section 14 to a diagonally adjacent switching section 14, forexample running between the busses h2s, h2n or between the busses v2e,v2w.

In the embodiment described above, each ALU has two independent carryinputs vci, hci and a connected pair of carry outputs co. If required,the ALUs may be arranged to deal with two types of carry: a fast carrybetween adjacent ALUs which may be of particular use for multi-bitadding operations; and a slow carry which can be routed more flexiblyand may be of particular use for digital serial arithmetic. The fastcarry might be arranged in a similar manner to that described above withreference to the drawings, whereas the slow carry might employprogrammable switches in the switching sections 14 between the carryconductor and particular bits of the 4-bit busses.

In the embodiment described above, particular bit widths, sizes ofswitching section and sizes of array have been mentioned, but it shouldbe noted that all of these values may be changed as appropriate. Also,the programmable switches 16, 18, 20 have been described as beingdisposed at particular locations in each switching section 14, but otherlocations may be used as required and desired.

In the embodiment described above, the array is two-dimensional, but theprinciples of the invention are also applicable to three-dimensionalarrays, for example by providing a stack of the arrays described above,with the switching sections in adjacent layers staggered with respect toeach other. The stack might include just two layers, but preferably atleast three layers, and the number of layers is preferably a power oftwo.

In the embodiment described above, the memory cells 24 can be isolatedby the gates 16 g, 18 g, 20 g from the switches which they control sothat the memory cells can be use d for other purposes, that is put inthe “user plane”. The ENABLE signal memory cells, however, cannot betransferred to the user plane. In an alternative embodiment, theswitches in a particular switching section 14 may be disconnectable fromthe remainder of the array by further switches in the busses at theboundary of that switching section 14, with the further switches beingcontrolled by a further memory cell which cannot be transferred to theuser plane.

Many other modifications and developments may also be made.

What is claimed is:
 1. An integrated circuit comprising a fieldprogrammable circuit region arranged as a generally rectangular array ofrows and columns of circuit areas and wherein: some of the circuit areaseach provide a respective processing unit for performing operations ondata on at least one respective input signal path to provide data on atleast one respective output signal path; others of the circuit areaseach provide a respective switching section; the processing units andthe switching sections are arranged alternately in each row and in eachcolumn and at least one of the processing units and a processing unitadjacent thereto each have a first input, a second input and an output;and each of a substantial proportion of the switching sections providesa programmable connection between at least some of the signal paths ofthose of the processing units adjacent that switching section in thesame column and in the same row, wherein a first type of the connectionsprovided by the switching sections are between such signal paths whichare generally collinear or parallel to each other, and wherein theoutput of one said processing unit is connectable by such a first typeof connection to the first or second input of the next processing unitin one direction in the same row, to the first or second input of thenext processing unit in the one direction in the same column, to thefirst or second input of the next processing unit in the oppositedirection in the same row, or to the first or second input of the nextprocessing unit in the opposite direction in the same column; andwherein the integrated circuit further comprises a plurality of interswitching section signal paths, each of which extends from a respectivefirst one of the switching sections to a respective second one of theswitching sections in the same row in a direction primarily generallyparallel to that row, or in the same column in a direction primarilygenerally parallel to that column, each of the inter switching sectionsignal paths being programmably connectable by the respective firstswitching section to others of the signal paths at that first switchingsection, and being programmably connectable by the respective secondswitching section to others of the signal paths at that second switchingsection.
 2. An integrated circuit as claimed in claim 1, wherein theoutput of said one processing unit is connectable: by such a first typeof connection to the first input of the next processing unit in onedirection in the same row; by such a first type of connection to thefirst input of the next processing unit in the one direction in the samecolumn; by such a first type of connection to the second input of thenext processing unit in the opposite direction in the same row; and bysuch a first type of connection to the second input of the nextprocessing unit in the opposite direction in the same column.
 3. Anintegrated circuit comprising a field programmable circuit regionarranged as a generally rectangular array of rows and columns of circuitareas and wherein: some of the circuit areas each provide a respectiveprocessing unit for performing operations on data on at least onerespective input signal path to provide data on at least one respectiveoutput signal path; others of the circuit areas each provide arespective switching section; the processing units and the switchingsections are arranged alternately in each row and in each column, and atleast one of the processing units and a processing unit adjacent theretoeach have a first input, a second input and an output; and each of asubstantial proportion of the switching sections provides a programmableconnection between at least some of the signal paths of those of theprocessing units adjacent that switching section in the same column andin the same row, wherein a second type of the connections provided bythe switching sections are between such signal paths which are generallyorthogonal to each other, wherein the output of one said processing unitis connectable by such a second type of connection in the same column tothe first or second input of the diagonally adjacent processing unit insaid one row direction and said one column direction, in the same row tothe first or second input of the diagonally adjacent processing unit insaid opposite row direction and said one column direction, in the samecolumn to the first or second input of the diagonally adjacentprocessing unit in said opposite row direction and said opposite columndirection, and in the same row to the first or second input of thediagonally adjacent processing unit in said one row direction and saidopposite column direction, and wherein the integrated circuit furthercomprises a plurality of inter switching section signal paths, each ofwhich extends from a respective first one of the switching sections to arespective second one of the switching sections in the same row in adirection primarily generally parallel to that row, or in the samecolumn in a direction primarily generally parallel to that column, eachof the inter switching section signal paths being programmablyconnectable by the respective first switching section to others of thesignal paths at that first switching section, and being programmablyconnectable by the respective second switching section to others of thesignal paths at that second switching section.
 4. An integrated circuitas claimed in claim 3, wherein the output of said one processing unit isconnectable: by such a second type of connection in the same column tothe first input of the diagonally adjacent processing unit in said onerow direction and said one column direction; by such a second type ofconnection in the same row to the first input of the diagonally adjacentprocessing unit in said opposite row direction and said one columndirection; by such a second type of connection in the same column to thesecond input of the diagonally adjacent processing unit in said oppositerow direction and said opposite column direction; and by such a secondtype of connection in the same row to the second input of the diagonallyadjacent processing unit in said one row direction and said oppositecolumn direction.
 5. An integrated circuit comprising a fieldprogrammable circuit region arranged as a generally rectangular array ofrows and columns of circuit areas and wherein: some of the circuit areaseach provide a respective processing unit for performing operations ondata on at least one respective input signal path to provide data on atleast one respective output signal path; others of the circuit areaseach provide a respective switching section; the processing units andthe switching sections are arranged alternatively in each row and ineach column; and each of a substantial proportion of the switchingsections provides a programmable connection between at least some of thesignal paths of those of the processing units adjacent that switchingsection in the same column and in the same row; and wherein theintegrated circuit further comprises a plurality of inter switchingsection signal paths, each of which extends from a respective first oneof the switching sections to a respective second one of the switchingsections in the same row in a direction primarily generally parallel tothat row, or in the same column in a direction primarily generallyparallel to that column, each of the inter switching section signalpaths being programmably connectable by the respective first switchingsection to others of the signal paths at that first switching section,and being programmably connectable by the respective second switchingsection to others of the signal paths at that second switching section,wherein for one type of the inter switching section signal paths, thereare no such switching sections in the respective row or column betweenthe respective first and second switching sections.
 6. An integratedcircuit as claimed in claim 5, wherein for another type of the interswitching section signal paths, the respective first and secondswitching sections have a number of other such switching sectionstherebetween in the respective row or column.
 7. An integrated circuitas claimed in claim 6, wherein for a further type of the inter switchingsection signal paths, each signal path has a spine extending in adirection generally parallel to the respective row or column and firstand second end portions each extending in a direction generallyorthogonal to the respective row or column and interconnecting the spineportion and the respective first and second switching sections,respectively.
 8. An integrated circuit as claimed in claim 5, whereinfor a further type of the inter switching section signal paths, eachsignal path has a spine extending in a direction generally parallel tothe respective row or column and first and second end portions eachextending in a direction generally orthogonal to the respective row orcolumn and interconnecting the spine portion and the respective firstand second switching sections, respectively.
 9. An integrated circuit asclaimed in claim 5, wherein for a further type of the inter switchingsection signal paths, each signal path has a spine extending in adirection generally parallel to the respective row or column and firstand second end portions each extending in a direction generallyorthogonal to the respective row or column and interconnecting the spineportion and the respective first and second switching sections,respectively.
 10. An integrated circuit comprising a field programmablecircuit region arranged as a generally rectangular array of rows andcolumns of circuit areas and wherein: some of the circuit areas eachprovide a respective processing unit for performing operations on dataon at least one respective input signal path to provide data on at leastone respective output signal path; others of the circuit areas eachprovide a respective switching section; the processing units and theswitching sections are arranged alternatively in each row and in eachcolumn; and each of a substantial proportion of the switching sectionsprovides a programmable connection between at least some of the signalpaths of those of the processing units adjacent that switching sectionin the same column and in the same row; and wherein the integratedcircuit further comprises a plurality of inter switching section signalpaths, each of which extends from a respective first one of theswitching sections to a respective second one of the switching sectionsin the same row in a direction primarily generally parallel to that row,or in the same column in a direction primarily generally parallel tothat column, each of the inter switching section signal paths beingprogrammably connectable by the respective first switching section toothers of the signal paths at that first switching section, and beingprogrammably connectable by the respective second switching section toothers of the signal paths at that second switching section, wherein fora further type of the inter switching section signal paths, each signalpath has a spine extending in a direction generally parallel to therespective row or column and first and second end portions eachextending in a direction generally orthogonal to the respective row orcolumn and interconnecting the spine portion and the respective firstand second switching sections, respectively.
 11. An integrated circuitas claimed in claim 10, wherein for at least some of the inter switchingsection signal paths of said further type, the respective first andsecond switching sections have a number of other such switching sectionstherebetween in the respective row or column.
 12. An integrated circuitas claimed in claim 11, wherein at least some of said numbers are eachone less than a power of two.
 13. An integrated circuit as claimed inclaim 11, wherein at least some of the inter switching section signalpaths of said further type each have at least one tap portion extendingin a direction generally orthogonal to the respective row or column andinterconnecting the spine portion and a respective such other switchingsection.
 14. An integrated circuit comprising a field programmablecircuit region arranged as a generally rectangular array of rows andcolumns of circuit areas and wherein: some of the circuit areas eachprovide a respective processing unit for performing operations on dataon at least one respective input signal path to provide data on at leastone respective output signal path; others of the circuit areas eachprovide a respective switching section; the processing units and theswitching sections are arranged alternatively in each row and in eachcolumn; and each of a substantial proportion of the switching sectionsprovides a programmable connection between at least some of the signalpaths of those of the processing units adjacent that switching sectionin the same column and in the same row: and wherein the integratedcircuit further comprises a plurality of inter switching section signalpaths, each of which extends from a respective first one of theswitching sections to a respective second one of the switching sectionsin the same row in a direction primarily generally parallel to that row,or in the same column in a direction primarily generally parallel tothat column, each of the inter switching section signal paths beingprogrammably connectable by the respective first switching section toothers of the signal paths at that first switching section, and beingprogrammably connectable by the respective second switching section toothers of the signal paths at that second switching section, wherein foranother type of the inter switching section signal paths, the respectivefirst and second switching sections have a number of other suchswitching sections therebetween in the respective row or column, whereinat least some of said numbers are each one less than a power of two. 15.An integrated circuit comprising a field programmable circuit regionarranged as a generally rectangular array of rows and columns of circuitareas and wherein: some of the circuit areas each provide a respectiveprocessing unit for performing operations on data on at least onerespective input signal path to provide data on at least one respectiveoutput signal path; others of the circuit areas each provide arespective switching section; the processing units and the switchingsections are arranged alternatively in each row and in each column; andeach of a substantial proportion of the switching sections provides aprogrammable connection between at least some of the signal paths ofthose of the processing units adjacent that switching section in thesame column and in the same row; and wherein the integrated circuitfurther comprises a plurality of inter switching section signal paths,each of which extends from a respective first one of the switchingsections to a respective second one of the switching sections in thesame row in a direction primarily generally parallel to that row, or inthe same column in a direction primarily generally parallel to thatcolumn, each of the inter switching section signal paths beingprogrammably connectable by the respective first switching section toothers of the signal paths at that first switching section, and beingprogrammably connectable by the respective second switching section toothers of the signal paths at that second switching section, wherein atleast one of the processing units is an arithmetic logic unit.
 16. Anintegrated circuit as claimed in claim 15, wherein at least one of theprocessing units has a plural-bit input and/or a plural-bit output, andwherein at least some of the signal paths are provided by respectiveplural-bit busses.
 17. An integrated circuit as claimed in claim 15,wherein all of the switching sections are so arranged to provide suchprogrammable connections.
 18. An integrated circuit as claimed in claim15, wherein at least one of the processing units and the processingunits adjacent thereto each have a first input, a second input and anoutput.
 19. An integrated circuit as claimed in claim 15, wherein afirst type of the connections provided by the switching sections arebetween such signal paths which are generally collinear with or parallelto each other.
 20. An integrated circuit as claimed in claim 19, whereinthe output of said one processing unit is connectable: by such a firsttype of connection to the first input of the next processing unit in onedirection in the same row; by such a first type of connection to thefirst input of the next processing unit in the one direction in the samecolumn; by such a first type of connection to the second input of thenext processing unit in the opposite direction in the same row; and bysuch a first type of connection to the second input of the nextprocessing unit in the opposite direction in the same column.
 21. Anintegrated circuit as claimed in claim 19, wherein a second type of theconnections provided by the switching sections are between such signalpaths which are generally orthogonal to each other.
 22. An integratedcircuit as claimed in claim 15, wherein a second type of the connectionsprovided by the switching sections are between such signal paths whichare generally orthogonal to each other.
 23. An integrated circuit asclaimed in claim 22, wherein at least one of the processing units andthe processing units adjacent thereto each have a first input, a secondinput and an output.
 24. An integrated circuit as claimed in claim 23,wherein the output of said one processing unit is connectable: by such asecond type of connection in the same column to the first input of thediagonally adjacent processing unit in said one row direction and saidone column direction; by such a second type of connection in the samerow to the first input of the diagonally adjacent processing unit insaid opposite row direction and said one column direction; by such asecond type of connection in the same column to the second input of thediagonally adjacent processing unit in said opposite row direction andsaid opposite column direction; and by such a second type of connectionin the same row to the second input of the diagonally adjacentprocessing unit in said one row direction and said opposite columndirection.
 25. An integrated circuit as claimed in claim 15, whereinsubstantially all of the input and output signal paths are oriented indirections substantially parallel to the rows or columns.
 26. Anintegrated circuit as claimed in claim 15, wherein for one type of theinter switching signal paths, there are no such switching sections inthe respective row or column between the respective first and secondswitching sections.
 27. An integrated circuit as claimed in claim 15,wherein for another type of the inter switching section signal paths,the respective first and second switching sections have a number ofother such switching sections therebetween in the respective row orcolumn.
 28. An integrated circuit as claimed in claim 15, wherein forone type of the inter switching section signal paths, there are no suchswitching sections in the respective row or column between therespective first and second switching sections, and for another type ofthe inter switching section signal paths, the respective first andsecond switching sections have a number of other such switching sectionstherebetween in the respective row or column.
 29. An integrated circuitas claimed in claim 15, wherein for a further type of the interswitching section signal paths, each signal path has a spine extendingin a direction generally parallel to the respective row or column andfirst and second end portions each extending in a direction generallyorthogonal to the respective row or column and interconnecting the spineportion and the respective first and second switching sections,respectively.
 30. An integrated circuit as claimed in claim 26, whereinfor a further type of the inter switching section signal paths, eachsignal path has a spine extending in a direction generally parallel tothe respective row or column and first and second end portions eachextending in a direction generally orthogonal to the respective row orcolumn and interconnecting the spine portion and the respective firstand second switching sections, respectively.
 31. An integrated circuitas claimed in claim 27, wherein for a further type of the interswitching section signal paths, each signal path has a spine extendingin a direction generally parallel to the respective row or column andfirst and second end portions each extending in a direction generallyorthogonal to the respective row or column and interconnecting the spineportion and the respective first and second switching sections,respectively.
 32. An integrated circuit as claimed in claim 28, whereinfor a further type of the inter switching section signal paths, eachsignal path has a spine extending in a direction generally parallel tothe respective row or column and first and second end portions eachextending in a direction generally orthogonal to the respective row orcolumn and interconnecting the spine portion and the respective firstand second switching sections, respectively.
 33. An integrated circuitas claimed in claim 29, wherein for at least some of the inter switchingsection signal paths of said further type, the respective first andsecond switching sections have a number of other such switching sectionstherebetween in the respective row or column.
 34. An integrated circuitas claimed in claim 27, wherein at least some of said numbers are eachone less than a power of two.
 35. An integrated circuit as claimed inclaim 33, wherein at least some of said numbers are each one less than apower of two.
 36. An integrated circuit as claimed in claim 33, whereinat least some of the inter switching section signal paths of saidfurther type each have at least one tap portion extending in a directiongenerally orthogonal to the respective row or column and interconnectingthe spine portion and a respective such other switching section.
 37. Anintegrated circuit as claimed in claim 15, wherein at least some of theswitching sections each include a respective register and/or bufferhaving an input and an output each switchably connectable to at leastsome of the signal paths at that switching section.